Asynchronous Counter

Following is a truth table for asynchronous counter.

C	B	A	Count
0	0	0	0
0	0	1	1
0	1	0	2
0	1	1	3
1	0	0	4
1	0	1	5
1	1	0	6
1	1	1	7
0	0	0	0

The basic idea is to keep the J and K inputs of each flip flop high, such that the flip flop will toggle with any negative clock transitions at its clock input. We then use AND gates to gate every second clock to flip flop B, every fourth clock to flip flop C and so on.

The clock is applied directly to flip flop A. Since the JK flip flop responds to a negative transition at the clock input and toggles when both the J and K inputs are high, flip flop A will change state with each negative clock transition.

Whenever A is high and AND gate X is enabled and a clock pulse is passed through the gate to the clock input of flip flop B.

Since AND gate Y is enabled and will transmit the clock to flip flop C only when both A and B are high, flip flop C changes state with every fourth negative clock transition.

Examination of the wave forms and the truth table reveals that this counter progresses upward in a natural binary sequence from count 000 up to 111, advancing one count with each negative clock transition. This is a mod-8, parallel or synchronous binary counter operating in the count up mode.

Ripple Counter