JK Flip-flop

JK Flip-flop is a modified version of SR flip-flop. The main difference is that both the inputs J and K are allowed to be 1 at the same time in JK flip-flop. When both J and K are 1 then the flip-flop complements its state. Thus the JK flip-flop resolves the undefined transition in the SR flip-flop.

The inputs J and K correspond to S and R in SR flip-flop respectively. That is, input J sets the device while the input K resets the device.

The letters J and K are merely for representing inputs. Unlike the symbols R and S in RS flip-flop the symbols J and K in JK flip-flop are not abbreviations.

As the flip-flop has clock input, it is called clocked JK flip-flop.

The outputs are Q and the complement of Q denoted by Q’. For example, if Q=0 then Q’ will be 1.

The figure(b) shows how JK flip-flop can be realized from SR flip-flop.

Logic diagram

Following figure(c) is logic diagram of a clocked JK flip-flop. The output Q is ANDed with input K and clock input CP. This will result in clearing the flip-flop during the clock pulse only if output Q was previously 1. Similarly, the output Q’ is ANDed with input J and clock input CP. This will result in flop-flop becomes set with clock pulse only if output Q’ was previously 1.

Characteristic table

Q(t)	J	K	Q(t+1)
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	1
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	0

Figure(d): Characteristic table

The characteristic table of JK flip-flop is almost the same as that of SR flip-flop. The only difference is that Q(t+1) is 0 when both the inputs J and K are 1. When J and K are 1, the clock pulse is transmitted through the AND gate whose input is connected to the output which is equal to 1. So, if Q=1 then upper AND gate produces 1 upon application of clock pulse and the flip-flop is cleared. If Q’=1 then lower AND gate produces 1 and the flip-flop is set. The output state of the flip-flop is complemented in either case.